RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
Required Ruby Version
>= 2.6
Authors
Taichi Ishitani
Versions
- 0.36.1 April 19, 2026 (75.5 KB)
- 0.36.0 January 07, 2026 (75.5 KB)
- 0.35.2 July 21, 2025 (16 KB)
- 0.35.1 June 01, 2025 (16 KB)
- 0.35.0 February 19, 2025 (16 KB)
- 0.26.2 June 13, 2022 (15.5 KB)
