RgGen is a code generator tool for SoC/IP/FPGA/RTL engineers. It will automatically generate source code for control/status registers, e.g. RTL, UVM RAL model, C header file, from its register map document. Also RgGen is customizable so you can build your specific generate tool.
Required Ruby Version
>= 2.3
Authors
Taichi Ishitani
Versions
- 0.36.1 April 19, 2026 (75.5 KB)
- 0.36.0 January 07, 2026 (75.5 KB)
- 0.35.2 July 21, 2025 (16 KB)
- 0.35.1 June 01, 2025 (16 KB)
- 0.35.0 February 19, 2025 (16 KB)
- 0.8.2 May 26, 2019 (71.5 KB)